Publications

Y. Zhang, J. Cheng, X. Liu, Z. Li, C.J. Li, J. Wu, L. Jiang, Y. Xie, J. Xu, W. Zhang (2026). VersaQ-3D: A Reconfigurable Accelerator Enabling Feed-Forward and Generalizable 3D Reconstruction via Versatile Quantization. arXiv preprint (2026).

X. Xiang, F. Tu (2026). VAR-Turbo: Unlocking the Potential of Visual Autoregressive Models through Dual Redundancy. International Symposium on High-Performance Computer Architecture (HPCA), Sydney, Australia.

Ceyu Xu, Yongji Wu, Xinyu Yang, Beidi Chen, Matthew Lentz, Danyang Zhuo, Lisa Wu Wills (2026). The Rise of Tensor Codecs. IEEE Micro Top Picks 2026.

Qijun Zhang, Chen Zhang, Zhuoshan Zhou, Haibo Wang, Zhe Zhou, Zhipeng Tu, Guangyu Sun, Zhiyao Xie, Yijia Diao, Zhigang Ji, Jingwen Leng, Guanghui He, Minyi Guo (2026). Tackling MoE Communication Bottleneck with Dynamic In-Switch Computing on Multi-GPUs. ISCA 2026.

Dimitrios Tsaras, Antoine Frederic Grosnit, Lei Chen, Zhiyao Xie, Haitham Bou Ammar, Mingxuan Yuan (2026). ShortCircuit: AlphaZero-Driven Generative Circuit Design. DAC 2026.

Ziyan Guo, Wenji Fang, Wenkai Li, Yuchao Wu, Shang Liu, Zhiyao Xie (2026). RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm. DAC 2026.

Jing Wang, Shang Liu, Hangan Zhou, Zhiyao Xie (2026). RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision. DAC 2026.

Z. Yang, D. Ding, Q. Ye, C. Huang, J. Chen, Y. Xie (2026). Reconfigurable Quantum Instruction Set Computers for High Performance Attainable on Hardware. ASPLOS 2026.

Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie (2026). ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework. ASP-DAC 2026.

Ceyu Xu, Xiangfeng Sun, Weihang Li, Chen Bai, Bangyan Wang, Mengming Li, Zhiyao Xie, Yuan Xie (2026). PF-LLM: Large Language Model Hinted Hardware Prefetching. ASPLOS 2026.

Z. He, Y. Wang, Z. Wu, H. Han, S. Wei, Y. Hu, C. Li, F. Tu, S. Yin (2026). MRCIM: A Many-Core Reconfigurable Computing-in-Memory Processor Combining CPU and Tensor Modes for NN Acceleration. IEEE Transactions on Circuits and Systems I (TCAS-I).

Yugao Zhu, Wenji Fang, Yao Lu, Shang Liu, Yanzhen Zhu, Qijun Zhang, Zhiyao Xie (2026). MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extension. TCAD 2026.

Wenkai Li, Yuchao Wu, Ziyan Guo, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie (2026). LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power. DAC 2026.

Yugao Zhu, Zhicheng Guo, Shang Liu, Mengming Li, Jing Wang, Zhiyao Xie (2026). IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning. DAC 2026.

Mengming Li, Chenlu Miao, Buqing Xu, Qijun Zhang, Xiangfeng Sun, Ceyu Xu, Yuan Xie, Wenkai Li, Shang Liu, Zhiyao Xie (2026). ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses. ISCA 2026.

Z. He, Y. Wang, Z. Yue, Z. Wu, H. Han, S. Wei, Y. Hu, F. Tu, S. Yin (2026). HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture with Unified Low-Cost Iterative Error Correction. International Symposium on High-Performance Computer Architecture (HPCA), Sydney, Australia.

C. Li, Y. Yin, C. Xue, Z. Wang, F. Bai, Y. Guo, X. Jiang, Q. Wu, Y. Xie, G. Sun (2026). Hardware-Software Co-design for 3D-DRAM-based LLM Serving Accelerator. arXiv preprint (2026).

Qijun Zhang, Yao Lu, Shang Liu, Mengming Li, Chen Zhang, Dongbo Wang, Zhiyao Xie (2026). G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs. DAC 2026.

Jay Zhe-an Mok, Qijun Zhang, Zhiyao Xie (2026). FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applications. DAC 2026.

Jiaao Ma, Ceyu Xu, Ning Liang, Lisa Wu Wills (2026). FlashTFHE: A Scalable Architecture for Efficient Multi-bit Fully Homomorphic Encryption. ISCA 2026.

Y. Wang, Z. He, C. Zhao, Z. Wu, M. Gao, H. Han, S. Wei, Y. Hu, F. Tu, S. Yin (2026). ETCIM: Error-Tolerant Digital CIM Processor with Redundancy-Free Hard Error Repair and Run-Time Soft Error Correction. IEEE Journal of Solid-State Circuits (JSSC).

R. Guo, L. Wang, X. Chen, K. Jiang, Z. Yue, H. Han, Y. Wang, F. Tu, S. Wei, Y. Hu, S. Yin (2026). Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising-similarity for Diffusion Models. IEEE Journal of Solid-State Circuits (JSSC).

Jinming Ge, Linfeng Du, Likith Anaparty, Shangkun Li, Tingyuan Liang, Afzal Ahmad, Vivek Chaturvedi, Sharad Sinha, Zhiyao Xie, Jiang Xu, Wei Zhang (2026). DAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning. DATE 2026.

J. Chen, Z. Xuan, Y. Li, Z. Yan, Z. Li, Y-F. Yung, Y. Deng, X. Huo, C-Y. Tsui, K-T. Cheng, F. Tu (2026). D2CIM: A 28nm 53.3 TFLOPS/W Decoding Digital CIM Macro for Efficient FlashMLA-based LLM Inference. Custom Integrated Circuits Conference (CICC), Seattle, USA.

Yao Lu, Zhicheng Guo, Qijun Zhang, Shang Liu, Wenji Fang, Wenkai Li, Zhiyao Xie (2026). COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging. DAC 2026.

Yugao Zhu, Zhicheng Guo, Yuchao Wu, Mengming Li, Jing Wang, Zhiyao Xie (2026). ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning. DAC 2026.

Z. Chen, Z. Li, L. Liang, X. Fan, X. Wang, Q. Liu, Z. Gu, Y. Lu, Y. Zhao, P. Qiu, Y. Xie (2026). ALOHA: Accelerating Leveled Fully Homomorphic Encryption with Cryptography-Specific Architectures. ACM Transactions on Architecture and Code Optimization 2026.

Wenkai Li, Yao Lu, Wenji Fang, Yugao Zhu, Ziyan Guo, Jing Wang, Mengming Li, Qijun Zhang, Zhiyao Xie (2026). A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis. TCAD 2026.

C. Li, C. Xue, Y. Ren, X. Dong, Y. Cheng, Y. Hu, F. Bai, Y. Guo, X. Jiang, Q. Wu, Y. Xie (2026). A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators. arXiv preprint (2026).

P. Dong, Y. Tan, X. Liu, P. Luo, Y. Liu, D. Pang, S. Ma, X. Huang, S-Y. Liu, D. Zhang, Z. Lu, L. Liang, C-Y. Tsui, F. Tu, L. Zhao, K-T. Cheng (2026). A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding. International Solid-State Circuits Conference (ISSCC), San Francisco, USA.

Z. He, Y. Wang, Z. Yue, Z. Wu, Y. Hu, F. Tu, S. Yin (2026). [Forthcoming] Symposium on VLSI Technology and Circuits (VLSI) 2026. Symposium on VLSI Technology and Circuits (VLSI), Honolulu, USA.

Y. Zhang, S. Sinha, J. Xu, W. Zhang (2025). UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHE. DATE 2025.

T. Xie, Z. Zhu, B. Li, Y. He, C. Li, G. Sun, H. Yang, Y. Xie, Y. Wang (2025). UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures. HPCA 2025.

Chaojian Li, Sixu Li, Linrui Jiang, Jingqun Zhang, Yingyan (Celine) Lin (2025). Uni-Render: A Unified Accelerator for Real-Time Rendering Across Diverse Neural Renderers. HPCA 2025.

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie (2025). Transferable Pre-Synthesis PPA Estimation for RTL Designs with Data Augmentation Techniques. TCAD 2025.

G. Huang, H. Li, L. Qin, J. Huang, Y. Kang, Y. Ding, Y. Xie (2025). TRACI: Network Acceleration of Input-Dynamic Communication for Large-Scale Deep Learning Recommendation Model. ISCA 2025.

Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie (2025). Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. ASP-DAC 2025.

Linshen Liu, Boyan Su, Junyue Jiang, Guanlin Wu, Cong Guo, Ceyu Xu, Hao Frank Yang (2025). Towards Accurate and Efficient 3D Object Detection for Autonomous Driving: A Mixture of Experts Computing System on Edge. ICCV 2025.

Y. Wang, Z. Wu, W. Wu, L. Liu, Y. Hu, S. Wei, F. Tu, S. Yin (2025). TensorCIM: Digital Computing-In-Memory Tensor Processor with Multi-Chip-Module-based Architecture for Beyond-NN Acceleration. IEEE Journal of Solid-State Circuits (JSSC).

E. Li, Z. Lin, S. Sinha, W. Zhang (2025). TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms. FPGA 2025.

Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie (2025). SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. DAC 2025.

Shang Liu, Yao Lu, Wenji Fang, Jing Wang, Zhiyao Xie (2025). SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models. EMNLP 2025.

M. Wu, M. Yan, W. Li, X. Ye, D. Fan, Y. Xie (2025). Survey on Characterizing and Understanding GNNs from a Computer Architecture Perspective. IEEE Transactions on Parallel and Distributed Systems 2025.

F. Zhang, Z. Gu, Y. Li, C. Hong, Z. Chen, Y. Wang, Y. Lu, M. Li, L. Liu, Y. Xie (2025). STEED: Space and Time-efficient Encrypted Database Using FHE. IEEE Transactions on Dependable and Secure Computing 2025.

Y. Zhang, J. Liang, J. Peng, J. Xu, W. Zhang (2025). SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices. DATE 2025.

Mengming Li, Wenji Fang, Qijun Zhang, Zhiyao Xie (2025). SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model. ISEDA 2025.

Yikang Ouyang, Yuchao Wu, Dongsheng Zuo, Subhendu Roy, Tinghuan Chen, Zhiyao Xie, Yuzhe Ma (2025). SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization. ASP-DAC 2025.

J. Cheng, W. Li, J. Luo, X. Tang, Z. He, J. Wu, Y. Zou, W. Zhang (2025). Scale, Don't Fine-tune: Guiding Multimodal LLMs for Efficient Visual Place Recognition at Test-Time. IFAC-PapersOnLine 2025.

Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie (2025). RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. TCAD 2025.

L. Yan, X. Zhao, B. Yang, Y. Wu, G. Dai, J. Li, C-Y. Tsui, K-T. Cheng, Y. Zhang, F. Tu (2025). Robotic Computing System and Embodied AI Evolution: An Algorithm-Hardware Co-Design Perspective. Journal of Semiconductors (JOS).

J. Deng, X. Tang, J. Zhang, Y. Li, L. Zhang, B. Han, H. He, F. Tu, S. Wei, Y. Hu, S. Yin (2025). Rethinking Control Flow in Spatial Architectures: Insights into Control Flow Plane Design. IEEE Transactions on Computers (TC).

Z. Yang, D. Ding, Q. Ye, C. Huang, J. Chen, Y. Xie (2025). ReQISC: A Reconfigurable Quantum Computer Microarchitecture and Compiler Co-Design. arXiv preprint (2025).

H. Wang, Z. Zhu, T. Zhao, Y. Xiang, Z. Wang, J. Yu, H. Yang, Y. Xie, Y. Wang (2025). REACT3D: Real-time Edge Accelerator for Incremental Training in 3D Gaussian Splatting based SLAM Systems. MICRO 2025.

Z. Yang, K. Zhang, X. Tian, X. Ren, Y. Liu, Y. Li, D. Ding, J. Chen, Y. Xie (2025). Qubit Mapping and Routing tailored to Advanced Quantum ISAs: Not as Costly as You Think. arXiv preprint (2025).

J. Huang, Y. Chen, Z. Wang, C.J. Hughes, Y. Ding, Y. Xie (2025). Push Multicast: A Speculative and Coherent Interconnect for Mitigating Manycore CPU Communication Bottleneck. HPCA 2025.

Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie (2025). Profile-Guided Temporal Prefetching. ISCA 2025.

Chen-Chia Chang, Wan-Hsuan Lin, Jingyu Pan, Guanglei Zhou, Zhiyao Xie, Jiang Hu, Yiran Chen (2025). PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection. ASP-DAC 2025.

Qijun Zhang, Zhiyao Xie (2025). Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations. ASP-DAC 2025.

J. Chen, T-C. Pang, Y-F. Yung, Y. Deng, A. Yin, X. Huo, L. Liang, Z. Wang, C-Y. Tsui, K-T. Cheng, F. Tu (2025). PipeDCIM: 28nm 115.11 TOPS/mm2xTOPS/W@1.24GHz Pipeline Digital CIM Macro with an Auto-Design Tool for Diverse High-Performance AI Scenarios. European Solid-State Electronics Research Conference (ESSERC), Munich, Germany.

Z. Yang, D. Ding, C. Zhu, J. Chen, Y. Xie (2025). Phoenix: Pauli-based High-level Optimization Engine for Instruction Execution on NISQ devices. DAC 2025.

Z. Jin, Y. Wang, Y. Chen, J. Xu, H. Yu, J. Chen, W. Lin, K. Fang, Y. Xie (2025). NVMePass: A Lightweight, High-performance and Scalable NVMe Virtualization Architecture with I/O Queues Passthrough. HPCA 2025.

Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie (2025). NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. DAC 2025.

T. Guan, Y. Guan, Z. Du, J. Ma, B. Tian, Z. Wang, T. Ma, Z. Liu, Y. Kong, Y. Xie (2025). Memtunnel: A CXL-based Rack-Scale Host Memory Pooling Architecture for Cloud Service. IEEE Transactions on Parallel and Distributed Systems 2025.

L. Liang, Z. Gu, F. Zhang, Z. Chen, X. Fan, D. Niu, M. Li, Z. Li, Z. Wang, Y. Xie (2025). Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator. ACM Transactions on Architecture and Code Optimization 2025.

Ceyu Xu, Yongji Wu, Xinyu Yang, Beidi Chen, Matthew Lentz, Danyang Zhuo, Lisa Wu Wills (2025). LLM.265: Video Codecs are Secretly Tensor Codecs. MICRO 2025.

Z. He, Z. Wu, R. Guo, L. Yan, H. Han, Y. Wang, S. Wei, Y. Hu, F. Tu, S. Yin (2025). LLM-CIM: A 28nm 126.7 TOPS/W Input-LUT-based Digital CIM Macro with Reconfigurable Matrix Multiplication and Nonlinear Operation Modes for LLMs. Symposium on VLSI Technology and Circuits (VLSI), Kyoto, Japan.

Z. Zhou, C. Lai, W. Zhang (2025). LLaMCAT: Optimizing Large Language Model Inference with Cache Arbitration and Throttling. ICPP 2025.

Cong Jiang, Haoyang Sun, Dan Feng, Zhiyao Xie, Benjamin Tan, Kang Liu (2025). LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization. TODAES 2025.

Mengming Li, Qijun Zhang, Yongqing Ren, Zhiyao Xie (2025). Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency. HPCA 2025.

Q. Wang, V.F. Pavlidis, X. Feng, R. Wang, W. Zhang, Y. Cheng (2025). Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated Circuits. ISVLSI 2025.

Jing Wang, Shang Liu, Yao Lu, Zhiyao Xie (2025). HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions. ICCAD 2025.

Y. Zhang, C. Ma, J. Ge, L. Jiang, J. Xu, W. Zhang (2025). HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantization. arXiv preprint (2025).

C. Li, Y. Yin, X. Wu, J. Zhu, Z. Gao, D. Niu, Q. Wu, X. Si, Y. Xie, C. Zhang, G. Sun (2025). H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference. ISCA 2025.

Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Zhiyao Xie (2025). GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment. ICCAD 2025.

X. Liu, J. Liang, L. Du, Y. Zhang, C. Ma, H. Fan, J. Xu, W. Zhang (2025). FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration. ICPP 2025.

Qijun Zhang, Mengming Li, Yao Lu, Zhiyao Xie (2025). FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling. ASP-DAC 2025.

Y. Wu, X. Wang, J. Chen, Z. Zhu, J. He, P. Dong, Y. Tan, X. Zhao, L. Chang, Y. Wang, F. Tu, C-Y. Tsui, K-T. Cheng (2025). Exploiting the Memory-Compute-Coupling Feature for CIM Accelerator Design Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

Z. He, Y. Wang, Z. Wu, S. Wei, Y. Hu, F. Tu, S. Yin (2025). ER-DCIM: Error-Resilient Digital CIM with Run-Time MAC-Cell Error Correction. International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, USA.

J. Dong, B. Luo, J. Zhang, P. Zhang, F. Feng, Y. Zhu, A. Liu, Z. Chen, Y. Shi, Y. Xie (2025). Enhancing Large-Scale AI Training Efficiency: The C4 Solution for Real-Time Anomaly Detection and Communication Optimization. HPCA 2025.

Dimitrios Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan (2025). ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring. DAC 2025.

X. Liu, J. Liang, Y. Zhang, L. Du, C. Ma, H. Yu, J. Xu, W. Zhang (2025). DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator. arXiv preprint (2025).

Z. Yue, Y. Wang, H. Wang, R. Guo, F. Tu, J. Yang, S. Wei, Y. Hu, S. Yin (2025). CV-CIM: A Hybrid Domain XOR-derived Similarity-aware Computation-in-memory Supporting Cost Volume Construction. IEEE Journal of Solid-State Circuits (JSSC).

H. Fan, Y. Wang, X. Zhou, S. Li, B. Zhao, Y. Lyu, J. Xu, W. Zhang (2025). CURE-Fuzz: Curiosity-Driven Reinforcement Learning for Agile Hardware Testing. ICCAD 2025.

S. Ma, J. Wu, Y. Tan, P. Dong, P. Luo, D. Pang, Y. Liu, X. Liu, L. Liang, K-T. Cheng, F. Tu (2025). CoXplorer: Multi-staged Co-exploration Framework for AI Model Compression and Accelerator Design. International Conference on Computer Aided Design (ICCAD), Munich, Germany.

Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie (2025). CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design. ICLR 2025.

Z. Wu, Z. He, B. Yang, Y. Wang, S. Wei, Y. Hu, F. Tu, S. Yin (2025). CELLA: A 28nm Compute-Memory Co-Optimized Real-Time Digital CIM-based Edge LLM Accelerator with 1.78ms-response in Prefill and 31.32 Token/s in Decoding. Symposium on VLSI Technology and Circuits (VLSI), Kyoto, Japan.

Qijun Zhang, Yao Lu, Mengming Li, Zhiyao Xie (2025). AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling. DAC 2025.

J. Liang, L. Du, X. Zhou, Z. Lin, J. Xu, W. Zhang (2025). AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs. DAC 2025.

Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie (2025). ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis. DAC 2025.

Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang (2025). AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. ASP-DAC 2025.

Jian Weng, Boyang Han, Derui Gao, Ruijie Gao, Wanning Zhang, An Zhong, Ceyu Xu, Jihao Xin, Yangzhixin Luo, Lisa Wu Wills, Marco Canini (2025). Assassyn: A Unified Abstraction for Architectural Simulation and Implementation. ISCA 2025.

Qijun Zhang, Yao Lu, Mengming Li, Shang Liu, Zhiyao Xie (2025). ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design. NeurIPS 2025 (Datasets and Benchmarks Track).

Qijun Zhang, Mengming Li, Andrea Mondelli, Zhiyao Xie (2025). An Architecture-Level CPU Modeling Framework for Power and Other Design Qualities. TCAD 2025.

C. Bai, X. Fan, Z. Zhu, W. Zhang, Y. Xie (2025). AccelStack: A Cost-Driven Analysis of 3D-Stacked LLM Accelerators. ICCAD 2025.

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie (2025). A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. ASP-DAC 2025.

P. Dong, Y. Tan, X. Liu, P. Luo, Y. Liu, L. Liang, Y. Zhou, D. Pang, M. Yung, D. Zhang, X. Huang, S-Y. Liu, Y. Wu, F. Tian, C-Y. Tsui, F. Tu, K-T. Cheng (2025). A 28nm 0.22uJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation. International Solid-State Circuits Conference (ISSCC), San Francisco, USA.