HKUST Computer Architecture Group
HKUST Computer Architecture Group
News
People
Events
Publications
Contact
Zhiyao Xie
Latest
A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis
ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning
COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging
DAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning
FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applications
G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning
LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power
MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extension
PF-LLM: Large Language Model Hinted Hardware Prefetching
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
ShortCircuit: AlphaZero-Driven Generative Circuit Design
Tackling MoE Communication Bottleneck with Dynamic In-Switch Computing on Multi-GPUs
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
An Architecture-Level CPU Modeling Framework for Power and Other Design Qualities
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations
PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection
Profile-Guided Temporal Prefetching
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage
Transferable Pre-Synthesis PPA Estimation for RTL Designs with Data Augmentation Techniques
Cite
×