HKUST Computer Architecture Group
HKUST Computer Architecture Group
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A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis
COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging
LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power
MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extension
RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
Profile-Guided Temporal Prefetching
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage
Transferable Pre-Synthesis PPA Estimation for RTL Designs with Data Augmentation Techniques
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