A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding

P. Dong, Y. Tan, X. Liu, P. Luo, Y. Liu, D. Pang, S. Ma, X. Huang, S-Y. Liu, D. Zhang, Z. Lu, L. Liang, C-Y. Tsui, F. Tu, L. Zhao, K-T. Cheng

January 2026

Abstract

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Type

Conference paper

Publication

International Solid-State Circuits Conference (ISSCC), San Francisco, USA