HKUST Computer Architecture Group

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Sat, 01 Jun 2030 13:00:00 +0000

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HKUST and Intel Establish Joint Laboratory to Focus on High-Efficiency Intelligent Computing

Thu, 05 Feb 2026 00:00:00 +0000

The Hong Kong University of Science and Technology (HKUST) and Intel Corporation announced the establishment of the HKUST–Intel Joint Laboratory. At the heart of the project is a three-year research program exploring high-efficiency near-memory computing (NMC) architectures to tackle the performance and energy-efficiency challenges of modern AI workloads. Through software–hardware co-design, the collaboration aims to inform the future development of intelligent devices and sustainable AI systems.

The signatories were Prof. Tim Kwan-Ting Cheng (Vice-President for Research and Development of HKUST) and Mr. Song Jiqiang (Director of Intel Labs China). Prof. Guo Yike (Provost of HKUST), Mr. Wang Zhicong (Chairman of Intel China), and Ms. Gabriela Cruz Thompson (Senior Director of University Research and Collaboration, Intel) witnessed the agreement.

Prof. Cheng noted that the launch of the Joint Lab aligns with HKUST’s Strategic Plan 2031, which identifies “AI, Future Computing, and Electronics” as a core research pillar. The lab will leverage HKUST’s combined strengths in software–hardware co-design and high-efficiency near-memory computing to jointly explore new pathways for intelligent computing.

The Joint Lab will be led by Prof. Yuan Xie, Fang Professor of Engineering and Chair Professor of the Department of Electronic and Computer Engineering at HKUST. It will focus on technical challenges in computing, memory, I/O bandwidth, and energy efficiency for intelligent devices.

[Forthcoming] Symposium on VLSI Technology and Circuits (VLSI) 2026

Thu, 01 Jan 2026 00:00:00 +0000

A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding

Thu, 01 Jan 2026 00:00:00 +0000

A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators

Thu, 01 Jan 2026 00:00:00 +0000

A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis

Thu, 01 Jan 2026 00:00:00 +0000

ALOHA: Accelerating Leveled Fully Homomorphic Encryption with Cryptography-Specific Architectures

Thu, 01 Jan 2026 00:00:00 +0000

ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning

Thu, 01 Jan 2026 00:00:00 +0000

COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging

Thu, 01 Jan 2026 00:00:00 +0000

D2CIM: A 28nm 53.3 TFLOPS/W Decoding Digital CIM Macro for Efficient FlashMLA-based LLM Inference

Thu, 01 Jan 2026 00:00:00 +0000

DAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning

Thu, 01 Jan 2026 00:00:00 +0000

Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising-similarity for Diffusion Models

Thu, 01 Jan 2026 00:00:00 +0000

ETCIM: Error-Tolerant Digital CIM Processor with Redundancy-Free Hard Error Repair and Run-Time Soft Error Correction

Thu, 01 Jan 2026 00:00:00 +0000

FlashTFHE: A Scalable Architecture for Efficient Multi-bit Fully Homomorphic Encryption

Thu, 01 Jan 2026 00:00:00 +0000

FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applications

Thu, 01 Jan 2026 00:00:00 +0000

G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs

Thu, 01 Jan 2026 00:00:00 +0000

Hardware-Software Co-design for 3D-DRAM-based LLM Serving Accelerator

Thu, 01 Jan 2026 00:00:00 +0000

HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture with Unified Low-Cost Iterative Error Correction

Thu, 01 Jan 2026 00:00:00 +0000

ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses

Thu, 01 Jan 2026 00:00:00 +0000

IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning

Thu, 01 Jan 2026 00:00:00 +0000

LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power

Thu, 01 Jan 2026 00:00:00 +0000

MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extension

Thu, 01 Jan 2026 00:00:00 +0000

MRCIM: A Many-Core Reconfigurable Computing-in-Memory Processor Combining CPU and Tensor Modes for NN Acceleration

Thu, 01 Jan 2026 00:00:00 +0000

PF-LLM: Large Language Model Hinted Hardware Prefetching

Thu, 01 Jan 2026 00:00:00 +0000

ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework

Thu, 01 Jan 2026 00:00:00 +0000

Reconfigurable Quantum Instruction Set Computers for High Performance Attainable on Hardware

Thu, 01 Jan 2026 00:00:00 +0000

RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision

Thu, 01 Jan 2026 00:00:00 +0000

RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

Thu, 01 Jan 2026 00:00:00 +0000

ShortCircuit: AlphaZero-Driven Generative Circuit Design

Thu, 01 Jan 2026 00:00:00 +0000

Tackling MoE Communication Bottleneck with Dynamic In-Switch Computing on Multi-GPUs

Thu, 01 Jan 2026 00:00:00 +0000

The Rise of Tensor Codecs

Thu, 01 Jan 2026 00:00:00 +0000

VAR-Turbo: Unlocking the Potential of Visual Autoregressive Models through Dual Redundancy

Thu, 01 Jan 2026 00:00:00 +0000

VersaQ-3D: A Reconfigurable Accelerator Enabling Feed-Forward and Generalizable 3D Reconstruction via Versatile Quantization

Thu, 01 Jan 2026 00:00:00 +0000

A 28nm 0.22uJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation