Zhiyao Xie | HKUST Computer Architecture Grouphttps://computer-arch-dev.hkust.edu.hk/author/zhiyao-xie/Zhiyao XieHugo Blox Builder (https://hugoblox.com)en-usThu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/media/icon_hu_7613a4a452ac7087.pngZhiyao Xiehttps://computer-arch-dev.hkust.edu.hk/author/zhiyao-xie/A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysishttps://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioninghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-compart-community-guided-post-coarsenin/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-compart-community-guided-post-coarsenin/COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaginghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-cool-a-cooling-aware-point-transformer/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-cool-a-cooling-aware-point-transformer/DAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learninghttps://computer-arch-dev.hkust.edu.hk/publication/date2026-dapo-design-structure-aware-pass-orderi/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/date2026-dapo-design-structure-aware-pass-orderi/FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applicationshttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-fsgen-agile-fused-and-sparse-accelerato/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-fsgen-agile-fused-and-sparse-accelerato/G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUshttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-g-power-architecture-level-gpu-power-mo/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-g-power-architecture-level-gpu-power-mo/ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesseshttps://computer-arch-dev.hkust.edu.hk/publication/isca2026-icp-exploiting-instruction-correlation/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2026-icp-exploiting-instruction-correlation/IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioninghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-impart-integration-of-memetic-operation/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-impart-integration-of-memetic-operation/LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Powerhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-leap-a-self-supervised-per-cycle-toggle/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-leap-a-self-supervised-per-cycle-toggle/MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extensionhttps://computer-arch-dev.hkust.edu.hk/publication/tcad2026-mfspart-a-generalized-partitioning-fram/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-mfspart-a-generalized-partitioning-fram/PF-LLM: Large Language Model Hinted Hardware Prefetchinghttps://computer-arch-dev.hkust.edu.hk/publication/asplos2026-pf-llm-large-language-model-hinted-hard/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asplos2026-pf-llm-large-language-model-hinted-hard/ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Frameworkhttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2026-readypower-a-reliable-interpretable-a/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2026-readypower-a-reliable-interpretable-a/RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revisionhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-benchmt-dynamic-maintenance-of-rtl/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-benchmt-dynamic-maintenance-of-rtl/RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigmhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-sequencer-towards-scalable-rtl-timi/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-sequencer-towards-scalable-rtl-timi/ShortCircuit: AlphaZero-Driven Generative Circuit Designhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-shortcircuit-alphazero-driven-generativ/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-shortcircuit-alphazero-driven-generativ/Tackling MoE Communication Bottleneck with Dynamic In-Switch Computing on Multi-GPUshttps://computer-arch-dev.hkust.edu.hk/publication/isca2026-tackling-moe-communication-bottleneck-wi/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2026-tackling-moe-communication-bottleneck-wi/A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Taskshttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-a-self-supervised-pre-trained-and-cros/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-a-self-supervised-pre-trained-and-cros/An Architecture-Level CPU Modeling Framework for Power and Other Design Qualitieshttps://computer-arch-dev.hkust.edu.hk/publication/tcad2025-an-architecture-level-cpu-modeling-frame/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-an-architecture-level-cpu-modeling-frame/ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Designhttps://computer-arch-dev.hkust.edu.hk/publication/neurip2025-archpower-dataset-for-architecture-leve/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/neurip2025-archpower-dataset-for-architecture-leve/AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMshttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-assertllm-generating-hardware-verificat/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-assertllm-generating-hardware-verificat/ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysishttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-atlas-a-self-supervised-and-cross-stage/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-atlas-a-self-supervised-and-cross-stage/AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decouplinghttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-autopower-automated-few-shot-architectu/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-autopower-automated-few-shot-architectu/CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Designhttps://computer-arch-dev.hkust.edu.hk/publication/iclr2025-circuitfusion-multimodal-circuit-repres/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iclr2025-circuitfusion-multimodal-circuit-repres/ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoringhttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-elf-efficient-logic-synthesis-by-prunin/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-elf-efficient-logic-synthesis-by-prunin/FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modelinghttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-firepower-towards-a-foundation-with-gen/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-firepower-towards-a-foundation-with-gen/GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmenthttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-geneda-towards-generative-netlist-funct/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-geneda-towards-generative-netlist-funct/HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutionshttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-hlsdebugger-identification-and-correcti/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-hlsdebugger-identification-and-correcti/Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiencyhttps://computer-arch-dev.hkust.edu.hk/publication/hpca2025-integrating-prefetcher-selection-with-dy/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/hpca2025-integrating-prefetcher-selection-with-dy/LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localizationhttps://computer-arch-dev.hkust.edu.hk/publication/todaes2025-lithoexp-explainable-two-stage-cnn-base/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/todaes2025-lithoexp-explainable-two-stage-cnn-base/NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphhttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-nettag-a-multimodal-rtl-and-layout-alig/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-nettag-a-multimodal-rtl-and-layout-alig/Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizationshttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-pointer-an-energy-efficient-reram-based/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-pointer-an-energy-efficient-reram-based/PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detectionhttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-pricing-privacy-preserving-circuit-data/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-pricing-privacy-preserving-circuit-data/Profile-Guided Temporal Prefetchinghttps://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Techniquehttps://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimizationhttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-smart-gpo-gate-level-sensitivity-measur/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-smart-gpo-gate-level-sensitivity-measur/SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Modelhttps://computer-arch-dev.hkust.edu.hk/publication/iseda2025-specllm-exploring-generation-and-review/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iseda2025-specllm-exploring-generation-and-review/SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Modelshttps://computer-arch-dev.hkust.edu.hk/publication/emnlp2025-sync-llm-generation-of-large-scale-synt/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/emnlp2025-sync-llm-generation-of-large-scale-synt/SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuitshttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-syncircuit-automated-generation-of-new/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-syncircuit-automated-generation-of-new/Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stagehttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-towards-big-data-in-ai-for-eda-research/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-towards-big-data-in-ai-for-eda-research/Transferable Pre-Synthesis PPA Estimation for RTL Designs with Data Augmentation Techniqueshttps://computer-arch-dev.hkust.edu.hk/publication/tcad2025-transferable-pre-synthesis-ppa-estimatio/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-transferable-pre-synthesis-ppa-estimatio/