Wenji Fang | HKUST Computer Architecture Grouphttps://computer-arch-dev.hkust.edu.hk/author/wenji-fang/Wenji FangHugo Blox Builder (https://hugoblox.com)en-usThu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/media/icon_hu_7613a4a452ac7087.pngWenji Fanghttps://computer-arch-dev.hkust.edu.hk/author/wenji-fang/A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysishttps://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaginghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-cool-a-cooling-aware-point-transformer/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-cool-a-cooling-aware-point-transformer/LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Powerhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-leap-a-self-supervised-per-cycle-toggle/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-leap-a-self-supervised-per-cycle-toggle/MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extensionhttps://computer-arch-dev.hkust.edu.hk/publication/tcad2026-mfspart-a-generalized-partitioning-fram/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-mfspart-a-generalized-partitioning-fram/RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigmhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-sequencer-towards-scalable-rtl-timi/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-sequencer-towards-scalable-rtl-timi/A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Taskshttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-a-self-supervised-pre-trained-and-cros/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-a-self-supervised-pre-trained-and-cros/AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMshttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-assertllm-generating-hardware-verificat/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-assertllm-generating-hardware-verificat/ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysishttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-atlas-a-self-supervised-and-cross-stage/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-atlas-a-self-supervised-and-cross-stage/CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Designhttps://computer-arch-dev.hkust.edu.hk/publication/iclr2025-circuitfusion-multimodal-circuit-repres/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iclr2025-circuitfusion-multimodal-circuit-repres/GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmenthttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-geneda-towards-generative-netlist-funct/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-geneda-towards-generative-netlist-funct/NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphhttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-nettag-a-multimodal-rtl-and-layout-alig/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-nettag-a-multimodal-rtl-and-layout-alig/Profile-Guided Temporal Prefetchinghttps://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Techniquehttps://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Modelhttps://computer-arch-dev.hkust.edu.hk/publication/iseda2025-specllm-exploring-generation-and-review/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iseda2025-specllm-exploring-generation-and-review/SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Modelshttps://computer-arch-dev.hkust.edu.hk/publication/emnlp2025-sync-llm-generation-of-large-scale-synt/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/emnlp2025-sync-llm-generation-of-large-scale-synt/SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuitshttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-syncircuit-automated-generation-of-new/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-syncircuit-automated-generation-of-new/Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stagehttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-towards-big-data-in-ai-for-eda-research/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-towards-big-data-in-ai-for-eda-research/Transferable Pre-Synthesis PPA Estimation for RTL Designs with Data Augmentation Techniqueshttps://computer-arch-dev.hkust.edu.hk/publication/tcad2025-transferable-pre-synthesis-ppa-estimatio/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-transferable-pre-synthesis-ppa-estimatio/