<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Qijun Zhang | HKUST Computer Architecture Group</title><link>https://computer-arch-dev.hkust.edu.hk/author/qijun-zhang/</link><atom:link href="https://computer-arch-dev.hkust.edu.hk/author/qijun-zhang/index.xml" rel="self" type="application/rss+xml"/><description>Qijun Zhang</description><generator>Hugo Blox Builder (https://hugoblox.com)</generator><language>en-us</language><lastBuildDate>Thu, 01 Jan 2026 00:00:00 +0000</lastBuildDate><image><url>https://computer-arch-dev.hkust.edu.hk/media/icon_hu_7613a4a452ac7087.png</url><title>Qijun Zhang</title><link>https://computer-arch-dev.hkust.edu.hk/author/qijun-zhang/</link></image><item><title>A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis</title><link>https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/</link><pubDate>Thu, 01 Jan 2026 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/</guid><description/></item><item><title>COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging</title><link>https://computer-arch-dev.hkust.edu.hk/publication/dac2026-cool-a-cooling-aware-point-transformer/</link><pubDate>Thu, 01 Jan 2026 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/dac2026-cool-a-cooling-aware-point-transformer/</guid><description/></item><item><title>FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applications</title><link>https://computer-arch-dev.hkust.edu.hk/publication/dac2026-fsgen-agile-fused-and-sparse-accelerato/</link><pubDate>Thu, 01 Jan 2026 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/dac2026-fsgen-agile-fused-and-sparse-accelerato/</guid><description/></item><item><title>G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs</title><link>https://computer-arch-dev.hkust.edu.hk/publication/dac2026-g-power-architecture-level-gpu-power-mo/</link><pubDate>Thu, 01 Jan 2026 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/dac2026-g-power-architecture-level-gpu-power-mo/</guid><description/></item><item><title>ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses</title><link>https://computer-arch-dev.hkust.edu.hk/publication/isca2026-icp-exploiting-instruction-correlation/</link><pubDate>Thu, 01 Jan 2026 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/isca2026-icp-exploiting-instruction-correlation/</guid><description/></item><item><title>MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extension</title><link>https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-mfspart-a-generalized-partitioning-fram/</link><pubDate>Thu, 01 Jan 2026 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-mfspart-a-generalized-partitioning-fram/</guid><description/></item><item><title>ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework</title><link>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2026-readypower-a-reliable-interpretable-a/</link><pubDate>Thu, 01 Jan 2026 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2026-readypower-a-reliable-interpretable-a/</guid><description/></item><item><title>Tackling MoE Communication Bottleneck with Dynamic In-Switch Computing on Multi-GPUs</title><link>https://computer-arch-dev.hkust.edu.hk/publication/isca2026-tackling-moe-communication-bottleneck-wi/</link><pubDate>Thu, 01 Jan 2026 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/isca2026-tackling-moe-communication-bottleneck-wi/</guid><description/></item><item><title>An Architecture-Level CPU Modeling Framework for Power and Other Design Qualities</title><link>https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-an-architecture-level-cpu-modeling-frame/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-an-architecture-level-cpu-modeling-frame/</guid><description/></item><item><title>ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design</title><link>https://computer-arch-dev.hkust.edu.hk/publication/neurip2025-archpower-dataset-for-architecture-leve/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/neurip2025-archpower-dataset-for-architecture-leve/</guid><description/></item><item><title>ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis</title><link>https://computer-arch-dev.hkust.edu.hk/publication/dac2025-atlas-a-self-supervised-and-cross-stage/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/dac2025-atlas-a-self-supervised-and-cross-stage/</guid><description/></item><item><title>AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling</title><link>https://computer-arch-dev.hkust.edu.hk/publication/dac2025-autopower-automated-few-shot-architectu/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/dac2025-autopower-automated-few-shot-architectu/</guid><description/></item><item><title>FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling</title><link>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-firepower-towards-a-foundation-with-gen/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-firepower-towards-a-foundation-with-gen/</guid><description/></item><item><title>Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency</title><link>https://computer-arch-dev.hkust.edu.hk/publication/hpca2025-integrating-prefetcher-selection-with-dy/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/hpca2025-integrating-prefetcher-selection-with-dy/</guid><description/></item><item><title>Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations</title><link>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-pointer-an-energy-efficient-reram-based/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-pointer-an-energy-efficient-reram-based/</guid><description/></item><item><title>Profile-Guided Temporal Prefetching</title><link>https://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/</guid><description/></item><item><title>RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique</title><link>https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/</guid><description/></item><item><title>SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model</title><link>https://computer-arch-dev.hkust.edu.hk/publication/iseda2025-specllm-exploring-generation-and-review/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/iseda2025-specllm-exploring-generation-and-review/</guid><description/></item><item><title>Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage</title><link>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-towards-big-data-in-ai-for-eda-research/</link><pubDate>Wed, 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